Multiplexing in digital transmission utilizes a pulse stuffing system. The pulse stuffing system synchronizes a plurality of signals that are different in transmission speed. To be more specific, a transmission-side device adjusts the insertion frequency of a stuffing pulse (also referred to as an “excessive pulse”) to be inserted into various kinds of signals to synchronize signals, and multiplexes signals into which the stuffing pulse is inserted to transmit to a reception-side device. At this time, the transmission-side device also transmits the information of the stuffing pulse to the reception-side device. The reception-side device removes, in demultiplexing signals received, the stuffing pulse from the signals to reproduce original signals. A transmission frame transmitted from the transmission-side device also includes control information such as over head (OH), forward error correction (FEC) in addition to the stuffing pulse.
Furthermore, the transmission-side device transmits a write enable (WE) signal for differentiating information except for actual transmission data (referred to as “pure signal” in some cases) such as the over head or the forward error correction and the pure signal to the reception-side device with the transmission frame. The reception-side device obtains a logical product of the WE signal and Line_CLK to extract a pulse string corresponding to pure communication information bits. Hereinafter, the pulse string in the above-mentioned state is referred to as “Gapped Clock” in some cases. Thereafter, the reception-side device smoothes the Gapped Clock to extract a clock for data reproduction.
In order to smooth the Gapped Clock, a digital phase locked loop (DPLL) having a low cut-off frequency is generally used. To be more specific, the cut-off frequency of the DPLL is set to several hertz or less (1 Hz or less, for example) to reduce the noise of the Gapped Clock thus obtaining the quality of a clock capable of being used for clock reproduction.
However, when the cut-off frequency is set to 1 Hz in starting each device, a pull-in time in the DPLL becomes long. Accordingly, at the time of starting the device, the following procedures are performed; that is, the DPLL is operated for a short period of time in a high speed operation mode using a high cut-off frequency of hundreds of hertz for pulling in, sufficiently pulled in until the target frequency and thereafter, the processing of the DPLL advances to an operation using the low cut-off frequency. The above-mentioned two-step operation ensures the reduction of the pull-in time and the attainment of excellent clock quality.
Furthermore, there is a technique for reducing the effect of noises of reference signals and reducing the pull-in time, the technique lowering the cut-off frequency of a low pass filter (LPF) to detect fluctuations in frequency and generating control data that follow the fluctuation in frequency; see Japanese Laid-open Patent Publication No. 2000-323982, for example.
However, in the Gapped Clock, a connection portion between the trailing “FEC” of a preceding frame and the leading “over head” of a succeeding frame constitutes a large gap. In this respect, in an operation mode using the low cut-off frequency steadily utilized, the cut-off frequency is low and hence, the DPLL fails to respond to a gap component. Therefore, a DPLL output constitutes a signal from which the gap component is removed; that is, a smoothed signal. In contrast, in an operation mode using a high cut-off frequency, the DPLL responds to the gap component. In this case, the DPLL output constitutes a signal containing the gap component. Accordingly, in the operation mode using the high cut-off frequency, the DPLL output is continuously influenced by the gap and hence, a frequency deviation is continuously caused.
Therefore, to consider a case where the above-mentioned two-step-operation technique is used, when changing to the operation mode using the low cut-off frequency at a timing that a large frequency deviation is caused, an operation mode is changed to the operation mode using the low cut-off frequency while maintaining the large frequency deviation. In this case, a large phase difference from a center frequency corresponding to the frequency deviation is processed with the low cut-off frequency thus causing the large phase difference corresponding to the frequency deviation over a prolonged period of time.
A data receiver includes first-in first-out (FIFO) for absorbing the difference between transmission reception amounts of data input and output. The FIFO is operated with a clock generated in the DPLL. When the phase difference from the center frequency is large, less data amount stored in the FIFO may result in communication failure. Therefore, when the phase difference is large, the data amount stored in the FIFO is increased. In that case, there exists the possibility that circuits become large or line delay occurs.
In this manner, in the above-mentioned technique, the use of the high cut-off frequency for high-speed pulling in may result in the increase of the phase difference and the increase of the capacity of the FIFO and hence, it is difficult to allow the high-speed pulling in and noise reduction simultaneously.
Furthermore, also in the technique lowering the cut-off frequency of the LPF to detect fluctuations in frequency and generating control data that follow the fluctuation in frequency, the increase in phase difference due to the effect of the gap when the operation mode is changed is unconsidered. Therefore, even when this technique is used, it is difficult to avoid the increase in phase difference and the increase in FIFO capacity due to the occurrence of the gap when the high cut-off frequency is used for performing the high-speed pulling in. That is, it is difficult to allow the high-speed pulling in and noise reduction simultaneously.